Books

3 results found
Title Authors Description OpenBook ID
RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA … RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA … Stuart Sutherland xxxi, 453 pages : 23 cm OL19822262W
IEEE standard Verilog hardware description language IEEE standard Verilog hardware description language Institute of Electrical and Electronics Engineers "The Verilog Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both… OL2062367W
Introduction to Logic Circuits & Logic Design with Verilog Introduction to Logic Circuits & Logic Design with Verilog Brock J. LaMeres 1 online resource (xvi, 459 pages) : OL20850550W