RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design

RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design

By Stuart Sutherland

Subjects: Computer simulation, Verilog (Computer hardware description language), Electronic digital computers -- Design and construction

Description: xxxi, 453 pages : 23 cm

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