Books
2 results foundTitle | Authors | Description | OpenBook ID | |
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RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA … | Stuart Sutherland | xxxi, 453 pages : 23 cm | OL19822262W |
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Applied computation theory | Raymond Tzuu-Yau Yeh | xiii, 624 p. : 24 cm | OL5860203W |