|
EDA ji shu yu VHDL
|
Pan,Song |
Ben shu nei rong bao kuo:EDA ji shu gai shu,VHDL cheng xu jie gou yu shu ju dui xiang,VHDL shu ju lei xing yu shun xu yu ju,Shi xu fang zhen yu ying jian shi xian,VHDL she ji shen ru,VHDL zhuang tai … |
OL20624144W |
|
Ji Suan Ji Dian Zi Dian Lu Ji Shu
|
Xiaoan Jiang |
Quan shu fen liang pian : di yi pian dian lu fen xi ji chu, di er pian mo ni dian zi ji shu. |
OL20660432W |
|
EDA ji shu
|
Jianghai Liu |
Ben shu xi tong di jie shao le ji yu FPGA/CPLD ying yong kai fa de EDA ji shu he ying jian miao shu yu yan VHDL, Jiang VHDL de ji chu zhi shi, Bian cheng ji qiao he shi yong fang fa yu shi ji gong ch… |
OL20660956W |
|
Yong VHDL she ji dian zi xian lu
|
Stefan Sjoholm |
Ben shu jie shao leVHDLjian jie, bing xingVHDL, shun xuVHDL, she ji ku, cheng xu bao yu zi cheng xu, jie gouVHDL, RAMyuROM, ce shi ji zhun, you xian zhuang tai ji deng nei rong. |
OL20661120W |