Multiple-valued programmable logic array minimization by simulated annealing

By Gerard W. Dueck

Subjects: LOGIC CIRCUITS, COMPUTER AIDED DESIGN, ANNEALING, COMPUTERIZED SIMULATION, COMPUTER PROGRAMS

Description: We propose a solution to the minimization problem of multiple-valued programmable logic arrays (PLA) that uses simulated annealing. The algorithm accepts a sum-of-products expression, divides and recombines the product terms, gradually progressing toward a minimal solution. The input expression can be user-specified or one produced by another heuristic. The process is termed simulated annealing because it has an analog in the statistical mechanical model of annealing in solids. That is, the slow cooling of certain solids results in a state of low energy, a crystalline state rather than an amorphous state that results from fast cooling. In a PLA, the crystalline state is analogous to a realization with a small number of product terms. Unlike recently studied minimization techniques (which are classified as direct cover methods), our technique manipulates product terms directly, breaking them up and joining them in different was while reducing the total number of product terms. Computer- aided design tool, multiple-valued logic, programmable logic array, heuristic minimization technique VLSI design tool.